By Olivier Jamin
This e-book discusses the trade-offs inquisitive about designing direct RF digitization receivers for the radio frequency and electronic sign processing domain names. A system-level framework is constructed, quantifying the correct impairments of the sign processing chain, via a accomplished system-level research. exact concentration is given to noise research (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion research, together with the effect of the sampling technique (low-pass, band-pass), research of time-interleaved ADC channel mismatches, sampling clock purity and electronic channel choice. The system-level framework defined is utilized to the layout of a cable multi-channel RF direct digitization receiver. An optimal RF sign conditioning, and a few algorithms (automatic achieve keep watch over loop, RF front-end amplitude equalization keep an eye on loop) are used to sit back the necessities of a 2.7GHz 11-bit ADC.
A two-chip implementation is gifted, utilizing BiCMOS and 65nm CMOS techniques, including the block and system-level size effects. Readers will enjoy the thoughts awarded, that are hugely aggressive, either when it comes to expense and RF functionality, whereas significantly decreasing energy consumption.
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Additional resources for Broadband Direct RF Digitization Receivers
In the example of Fig. 40 , a charge domain FIR filter is realized by integrating N successive samples of the RF waveform on two switched equal capacitors. This moving average FIR filter (all-ones coefficients) places notches at multiple frequencies of fs=N . The main obstacle for building wideband DT analog processing receivers is their intrinsic narrowband protection against aliasing: sinc response FIR filter attenuates potential interferers only across the notches BW located around k Á fs=N : Non-decimated FIR filter forms allow cascading of several filters prior to sampling rate reduction, in order to increase the notches BW.
3 illustrates the required Es/N0 as a function of the required BER, for several modulations. Es/N0 is homogeneous to a signal-to-noise ratio and is defined across the signal BW. 3 Sensitivity Test It is the minimum level at the receiver input, at which the receiver must be able to perform with the specified BER. 42 2 System-Level Design Framework for Direct RF Digitization RX 100 QPSK 16QAM 64QAM 10–1 BER 10–2 10–3 10–4 10–5 10–6 5 10 15 20 Es/N0 [dB] 25 30 Fig. 4 Adjacent and Blocker Test When a communication system has several users, and the channel conditions between users are different, the adjacent and nonadjacent channels can typically be much greater than the wanted channel, especially in wireless communications.
References [49, 50] reports 60 dB/90 dB attenuation of interferers across 50 MHz/10 MHz. Besides discrete analog signal processing in the time domain, research is also conducted on analog implementations of FFT [51, 52]: in the context of software radio systems using OFDM, the move from DSP-based FFT to analog-based FFT allows filtering narrowband interferers prior to analog-to-digital conversion, which leads to a more robust receiver. 13 μm (Fig. 41). 30 1 RF Receiver Architecture State of the Art N P1 P2 v(t) gm i(t) P2 P1 C C Fig.
Broadband Direct RF Digitization Receivers by Olivier Jamin